An active matrix type semiconductor device in which transistors as a switch element are arranged in a matrix shape may achieve a highly reliable device with a small size and low power, and therefore has been widely used. For example, a display apparatus using a liquid crystal or an electroluminescence (EL) material or a sensor device including a light receiving element such as a photodiode has been widely used as an input/output interface for a personal digital assistant, or the like, due to characteristics such as thinness and lightweight. In recent years, an active matrix type apparatus, in which the switch elements for driving display pixels or thin film transistors (TFTs) as an element for amplifying weak sensing signals are arranged on an array substrate which is an insulation substrate, and peripheral circuits for driving the TFTs arranged in an array, for example, scanning line driving circuits or signal line driving circuits include the TFTs formed on the same substrate as the switch elements, has been actively developed. Due to the above-described characteristics, the peripheral circuits may be integrated on the array substrate to extend an effective area of a display or sensing part active matrix, and reduce costs required for the peripheral circuits.
The TFTs arranged in the array as described above are N-type or P-type single conductive transistors in many cases. When the peripheral circuits include only the same single conductive transistors, processes such as mask exposure and impurity injection in a manufacturing process thereof may be made common with the TFTs arranged in the array, which leads to decrease manufacturing costs. An example in which the scanning line driving circuits (gate drivers) among the peripheral circuits are achieved by a connection of shift registers which include only the single conductive transistors is disclosed in Japanese Patent Laid-Open Publication No. 2006-106394.
In recent years, with the size and definition of a display screen becoming larger and higher, load capacity and load resistance of a gate line are also increased. Meanwhile, since a time to select the gate line, generally, one horizontal period is shortened, a demand for gate line driving capability of the gate driver is increased. While on the other hand, methods for extending a selection period by performing overlap scanning in which the selection period overlaps with a plurality of gate lines, to alleviate the demand for the driving capability are disclosed in Japanese Patent Laid-Open Publication No. 2006-106394 and WO2012/073467. The above-described methods are achieved by independently providing a first gate driver operated by two-phase clock of non-overlap clock signals CLK1 and CLK3 and a second gate driver operated by two-phase clock of non-overlap clock signals CLK2 and CLK4, and assigning overlap sections between the CLK1 and CLK3 and the CLK2 and CLK4. Herein, the gate driver includes only the N-type transistor. However, in the methods disclosed in Japanese Patent Laid-Open Publication No. 2006-106394 and WO 2012/073467, in order to extend the period in which the respective gate lines are selected by overlapping the selection period of the plurality of gate lines, there is a need to increase the number of clock signals.
Further, in the overlapping scanning, delaying a selection start of the gate, that is, a time required to start-up a gate line voltage when the single conductivity is provided as an N-type is alleviated by extending the selection period of the gate. On the other hand, a selection end of the gate, that is, falling of the gate line voltage has no effect to alleviate the delay, and when a falling time is delayed exceeding a switching (data idling) time of a data voltage put into a pixel, a data crosstalk, that is, a problem that a voltage which is mixed-up with a data voltage to be put into a next pixel is put occurs. A gate driver which executes the overlap scanning on a clock signal only by two phases is disclosed in Eunji Song and Hyoungsik Nam, SID2013 Digest, 35.4 (2013) (hereinafter, referred to as a non-Patent Document 1).